1. Technical Field
The present invention relates to a driver circuit for turning a power semiconductor device on and off.
2. Related Art
A driver circuit is necessary in order to cause a turning on and off of a power semiconductor device. The driver circuit has a pulse signal as an input, and amplifies the input as far as power needed for turning the power semiconductor device on and off.
One example of the driver circuit is shown in JP-A-2008-098920. The driver circuit of JP-A-2008-098920 includes an output buffer, formed of a high side output transistor (a p-channel field effect transistor) and a low side output transistor (an n-channel field effect transistor) that are turned on and off in a complementary way, and a dead time generator circuit for preventing the high side output transistor and low side output transistor from being turned on simultaneously.
A configuration wherein dead time is set in advance, as in the case of this driver circuit, is such that, when the output voltage of the driver circuit is set to be higher than the gate breakdown voltage of the high side output transistor and low side output transistor, a level shifter circuit for sending a gate signal to the high side output transistor is needed, and variation occurs in the transmission delay times of a high side output transistor drive signal and low side output transistor drive signal due to an action of the level shifter circuit. In order to combat this, it is necessary to secure dead time longer than the longest of the varying delay times, as a result of which, high speed switching becomes difficult. Also, as the circuit delay varies depending on the circuit configuration of the last stage of the dead time generator circuit and on operating conditions, a problem also occurs in that dead time setting is difficult.
Therefore, a circuit having a configuration wherein a turning off of the high side output transistor or low side output transistor is detected by monitoring the gate voltages thereof, the gate voltage of the high side output transistor is raised based on a downward change in the gate voltage of the low side output transistor, and the gate voltage of the low side output transistor is raised based on a downward change in the gate voltage of the high side output transistor, has been proposed (for example, refer to JP-A-2007-097348).
According to this configuration, after, for example, the high side output transistor is turned off, it is possible to swiftly cause the low side output transistor to be turned on, that is, to achieve a contraction of dead time.
However, when a turning off of the high side output transistor or low side output transistor is detected by monitoring the gate voltages thereof, as heretofore described, it is necessary to shift the levels of the transistor gate voltages.
That is, when, for example, it is detected that the high side output transistor has been turned off, it is necessary, taking the gate breakdown voltages of the high side output transistor and low side output transistor to be 5V and the amplitude of a voltage output from a series connection point of the transistors (the potential of this portion is the high side reference potential) to be 10V, to shift the gate voltage of the high side output transistor to a level appropriate to the low side circuit, and to transmit the voltage to the low side circuit.
FIG. 4 shows a heretofore known example of a level shifter circuit (for example, refer to Japanese Patent No. 3,384,399 (FIG. 5)). The level shifter circuit includes a shift down (level decreasing) circuit portion and a shift up (level increasing) circuit portion. The gate voltage of the high side output transistor output from an unshown driver circuit is input into an SOUT1 terminal of the shift down circuit portion.
The gate voltage is applied via a resistor Rp3 to a Zener diode (a p-channel field effect transistor used as a Zener diode) Zp1, clamped by the Zener diode Zp1, and applied to the gate of a high breakdown voltage p-channel transistor HVP. Resistors Rp1 and Rp2 are connected in series to the source and drain respectively of the transistor HVP, and a Zener diode Zp2 is connected in parallel to the resistor Rp2. Consequently, when the transistor HVP is turned on based on the gate voltage input into the SOUT1 terminal, a shifted down signal is output from a connection point of the resistor Rpt and the cathode of the Zener diode Zp2. This signal is clamped by the Zener diode Zp2.
As the shift up circuit portion has a configuration symmetrical with that of the shift down circuit portion, reference signs corresponding to components will be given, and a description of the components omitted.
When the level shifter circuit of Japanese Patent No. 3,384,399 (FIG. 5) is applied as it is to a driver circuit, the following kinds of problems occur.
A: As a large current continues to flow through the transistor HVP from a VDDHI terminal toward a VDDLC terminal during a period for which the high side output transistor of the driver circuit is in an on-state, accompanying power loss poses a problem.
B: It has been known heretofore that, when the gate voltage of the SOUT1 terminal momentarily changes to an H level due to noise or the like, and the high breakdown voltage p-channel transistor HVP is turned off, during a period for which the high side output transistor has to be in an on-state, the output of the shift down circuit portion immediately changes to an L level. In this case, as a driver circuit control circuit that receives the output signal of the shift down circuit portion mistakenly determines that the on-period of the high side output transistor has finished, there is concern that a malfunction, such as the low side output transistor being turned on and a shoot through current flowing, will occur.